1. Field of the Invention
The present invention is related to an oscillation control apparatus and an oscillator, which control amplitude and a level of an output signal.
2. Description of the Related Art
Since influences for lowering voltages of systems where oscillators are utilized are given to these oscillators, various sorts of development capable of lowering voltages of these oscillators have been carried out. For instance, although such oscillators have been available which can be operated in systems where a power supply voltage of 2.4 V has been employed, other oscillators operable in such systems that a power supply voltage of 1.8 V is employed are being developed. For instance, a patent publication 1 and a patent publication 2 have disclosed oscillators operable under low voltages.
FIG. 7 is a circuit diagram for indicating the oscillator disclosed in the patent publication 2. Since the oscillator shown in FIG. 7 has employed CMOS transistors M300 and M301 as an output amplifying circuit, a signal having such a waveform approximated to a rectangular waveform is outputted. However, since the signal having the waveform approximated to the rectangular waveform largely contains higher harmonic wave components, the oscillator represented in FIG. 7 is not suitably employed as an oscillator which is utilized in the communication field. This reason is given as follows: That is, the higher harmonic waves contained in the output signal may give an adverse influence to carrier signals.
As a result, an oscillator capable of reducing higher harmonic wave components contained in an output signal has been developed. In order to reduce the higher harmonic wave components, output waveforms must be approximated to SIN waves, or clipped SIN waves. To this end, an output amplifying circuit has been constructed not by the CMOS transistors shown in FIG. 7, but by source follower type NMOS transistors.
FIG. 8 is a circuit diagram for indicating an oscillator having the output amplifying circuit constructed of the source follower type NMOS transistors. The oscillator shown in FIG. 8 is equipped with two sets of regulators, namely, an internal power supply regulator 11, and an amplitude adjust-purpose regular 13. FIG. 9 is a circuit diagram for indicating an internal arrangement of the amplitude adjust-purpose regulator 13. As shown in FIG. 9, the amplitude adjust-purpose regulator 13 outputs a voltage “VREG2” controlled by a control unit 15. It should be noted that a maximum voltage that can be outputted by the amplitude adjust-purpose regulator 13 is such a voltage value obtained by subtracting a collector-to-emitter saturation voltage of a transistor Q1104 from a power supply voltage “Vcc.”
In the oscillator shown in FIG. 8, in order to output a signal having an amplitude (VH−VL) of 1 Vpp, 1.8 V is required as the voltage “VREG2” of the amplitude adjust-purpose regulator 13 (this reason will be explained later). In order that the amplitude adjust-purpose regulator 13 outputs the voltage “VREG2” which is lowered from the power supply voltage Vcc by the collector-to-emitter saturation voltage (namely, 0.2 V) of the transistor Q1104, the power supply voltage Vcc of 2.0 V (=1.8+0.2 V) is required to be applied to the amplitude adjust-purpose regulator 13. In other words, the oscillator shown in FIG. 8 cannot be properly operated under such a lower voltage than, or equal to 2.0 V.
Referring now to FIG. 10, a description is made of the reason why the voltage of 1.8 V is required as the above-described voltage “VREG2” of the amplitude adjust-purpose regulator 13 in order that the amplitude of the output signal becomes 1 Vpp. FIG. 10 is a diagram for graphically representing a relation among the amplitude Vpp of the output signal of the oscillator shown in FIG. 8, the voltage VREG2 of the amplitude adjust-purpose regulator 13, and the power supply voltage Vcc. A signal outputted from an output terminal “OUT” shown in FIG. 8 is changed in response to an output signal of an oscillating circuit 19. A phase of a gate voltage of an NMOS transistor M101 is the same phase of the output signal of the oscillating circuit 19. On the other hand, since an inverter amplifier “IA” has been provided between the oscillating circuit 19 and a gate of another NMOS transistor M100, a phase of this gate voltage of the NMOS transistor M100 is opposite to the phase of the output signal of the oscillating circuit 19. The phase of the signal outputted from the output terminal OUT is opposite to a phase of a voltage applied to the gate of the NMOS transistor M101.
A maximum voltage “VH” of a signal outputted from the output terminal OUT is expressed by the below-mentioned formula (1):
                                                        VH              =                              Vgmax                -                Vt                                                                                        =                                                VREG                  ⁢                                                                          ⁢                  2                                -                Vt                                                                        (        1        )            
It should be noted that symbol “Vmax” indicates a maximum value of a gate voltage of the NMOS transistor M100, and symbol “Vt” indicates a threshold voltage of the gate of the NMOS transistor M100.
The gate voltage of the NMOS transistor M100 is increased up to the power supply voltage VREG2 of the inverter amplifier IA (Vgmax=VREG2). As a consequence, the voltage VREG2 of the amplitude adjust-purpose regulator 13 corresponding to the power supply voltage of the power supply voltage VREG2 of the inverter amplifier IA is adjusted, so that the maximum voltage VH of the signal outputted from the output terminal OUT may be adjusted.
On the other hand, a minimum voltage “VL” of a signal outputted from the output terminal OUT is expressed by the below-mentioned formula (2):
                                                        VL              =                              VH                -                Vpp                                                                                        =                                                VREG                  ⁢                                                                          ⁢                  2                                -                Vt                -                Vpp                                                                        (        2        )            
However, the above-described minimum voltage VL is restricted by a drain-to-source saturation voltage VDS of the NMOS transistor M101 when the NMOS transistor M101 is under ON status, namely, when the gate voltage of the NMOS transistor M101 is in an H level.
In this case, assuming now that the minimum voltage VL is designed to be 0.1 V, in order that the signal outputted from the output terminal OUT has such an amplitude (=VH−VL) of 1 Vpp, the maximum voltage VH is required to be equal to 1.1 V (VH=1.1 V). As a consequence, since the voltage VREG2 of the amplitude adjust-purpose regulator 13 is equal to VH+Vt based upon the above-described formula (1), this voltage VREG2 is required to be 1.8V (=1.1+0.7 V).
It should be understood that, as previously described, since the voltage value obtained by subtracting the collector-to-emitter saturation voltage Vsat of the transistor Q1104 contained in the amplitude adjust-purpose regulator 13 from the power supply voltage Vcc becomes the voltage VREG2 of the amplitude adjust-purpose regulator 13, assuming now that the saturation voltage Vsat is equal to 0.2 V, such a power supply voltage Vcc of 2.0 V (=1.8+0.2 V) is required.
Patent Publication 1: JP-UM-A-59-096905
Patent Publication 2: JP-A-2007-53746
As previously described, the signal outputted from the oscillator shown in FIG. 7 contains the large amounts of higher harmonic wave components. Also, in accordance with the oscillator shown in FIG. 8, since the output amplifying circuit has been arranged by the source follower type NMOS transistors, the higher harmonic wave components of the output terminal are reduced, and on the other hand, the oscillator of FIG. 8 cannot be properly operated at the lower voltages than, or equal to 2.0 V in order to output the signal having the amplitude of 1 Vpp.